Doing your test development in the U.S. can significantly reduce your time-to-market.
Getting a new Integrated Circuit (IC) to market almost always takes longer than anticipated and developing an effective test process is frequently a meaningful contributor to that problem.
Test company experience shows that ~80% of new IC designs do not meet one or more of the major original design goals. The test process is where a company often finds out exactly what device they will actually be taking to market. The natural consequence of this “reconciliation” process is that the time it takes to get the new IC to market will vary proportionately to the number and severity of the differences between the IC’s intended design and reality.
The graphic below shows the test process as most IC development schedules show it – a linear process that is not overly long or complex.
In contrast, this is the way the process works in the real world.
The real process is an iterative, indeterminate, back and forth dialog between the test engineer and the design engineer. The process follows the above loop for every function and parameter that is not meeting the original design spec. Sometimes the design is robust and the number of times through the loop is only 30 or so. But sometimes the issues are more numerous and the number of iterations through the loop can go into the hundreds. Clearly, reducing the number of iterations – and the length of time each iteration takes – will decrease the time it takes to get the IC into the customer’s hands.
The goal of this iterative loop is achieving something called “Correlation” whereby the test engineer and the design engineer agree that the test process is satisfactorily assessing the performance and functionality of the new device.
As data is examined, test approaches debated and experiments run, the number of iterations through the loop, shown in Figure 2, continues to add up – frequently causing significant delays in getting the IC to market.
Even after correlation is initially achieved, the test development loop may need to be reentered. Correlation is initially achieved based on a set of tests that is a subset of all the possible combinations of the way a device can be used. Different customers in different markets supporting different applications can all use the device differently. Even the biggest semiconductor manufacturers can’t test for all the possible combinations of conditions that the device may see in the myriad applications it may end up in. Thus, as new failure mechanisms are discovered by end-customers, the test development and correlation “loop” is often reentered.
So how can we shorten this iterative test development and correlation loop? The answer to this question has been analyzed, researched and reported on in countless papers presented throughout the history of the semiconductor industry. However, one of the often-overlooked ways to make the test development process more efficient is to physically locate the test engineer and the design engineer as close as possible.
The reasoning is that the faster the inevitable iterations through the test development loop can occur, the faster correlation will be achieved and the faster the new device can be shipped in high volume. This physical colocation is not a new idea, but it is one that is more and more difficult to achieve with the migration of much of the silicon processing to Asia. While this migration has contributed to lower overall costs, is has also forced people farther apart physically – and for the highly interactive test development process, this can add significant time in getting to market.
One alternative that can significantly improve time to market is to do the test development, qualification and initial production at a supplier that is physically located near your development team. In particular, if you are a US based design team, working with a US based back-end service provider to achieve initial (and post-initial) production correlation can save valuable time to market. Then once the product is correlated and stable, let the Asian suppliers do what they do best – ship high volume production at low costs. This solution can be particularly appealing to the 1200 or so small to medium sized fabless semiconductor companies located across the globe that don’t command the same level of attention at Asian suppliers that the top semiconductor companies do.
The increase in the time to market resulting from the above iterative reality isn’t difficult to compute. Take the number of times that the loop in Figure 2 is circumnavigated and multiply by the extra time it takes to communicate over 8-12 time zones to Asia versus the time it takes to communicate 0-3 time zones in the US. Experience shows that the same amount of data that can traverse the test development loop in 24 hours between the US and Asia, can speed by in the US in as little as 3 hours.
Add to that the potential for language related delays, where the question being asked by the designer or the reply from the Asian test engineer is not clearly understood, and the additional time to iterate with Asia can easily double.
What does that mean for time to market? Let’s take two examples: one at 30 iterations through the “loop” in Figure 2 (probably the best that can be hoped for even with a simple device) and one at 150 iterations through the loop (probably towards the high end of the iterative spectrum). Let’s also assume that we are only working Monday through Friday from 8:00 AM to 8:00 PM.
So in the US, 30 needed iterations divided by a conservative 3 iterations per day is 10 working days or two 5-day work weeks. In Asia it will be 30 needed iterations divided by 1 iteration per day equals 30 working days or six 5-day workweeks. What would typically take 2 weeks in the US just took 6 weeks in Asia – and if the language issue multiplier is present it could make the delay 9 to 12 weeks.
If you run the same figure for the 150-iteration loop, you get a US time of 10 weeks and an Asian time of 30 weeks plus any language multipliers! And this doesn’t include additional correlation iterations due to qualification failure reconciliation or iterations due to initial customer failures. These are meaningful differences in time to market for any company.
To be fair, there are good suppliers in Asia that are competent at test development and qualification who can do a great job. You just need to know who they are and that you will get their “A-Team” working on your project throughout its introduction and initial production. Even then the time zone and language barriers will cause a certain amount of additional delay – it is nearly unavoidable.
So if you are a US based fabless semiconductor company interested in getting to market faster rather than slower, there are several good alternatives right here in the US that can help you.